Manufacturing increasingly advanced semiconductors requires that the minimum size of the features on the chips decrease every generation. As the critical feature sizes on semiconductors start to shrink beyond the minimum wavelength of the light (193 nm-248 nm), a variety of techniques such as larger lenses and multi-patterning can be used to make sub-wavelength features. One promising class of techniques, pitch splitting processes, in particular Sidewall Image Transfer (SIT), are among the best candidates for 20 nm and beyond technology, where conventional single exposure lithography will not work.
These pitch splitting processes use multiple lithography steps in order to produce the semiconductors. To simplify and minimize the complexity of the design, the chip designers can draw final wafer images as a single layer and those layouts can be decomposed into several different layers and patterns during the mask data preparation. Decomposing layouts is a calculation intensive process, and massive amounts of processing time are required in order to decompose the design layout into the photomask layers.
The above-described deficiencies of decomposing layouts for preparing photomasks are merely intended to provide an overview of some problems of current technology, and are not intended to be exhaustive. Other problems with the state of the art, and corresponding benefits of some of the various non-limiting embodiments described herein, may become further apparent upon review of the following detailed description.